The present invention relates generally to redundancy circuits for semiconductor memory devices, and more particularly to redundancy address setting circuits for semiconductor memories.
The storage capacity of semiconductor memory devices has continued to increase at a remarkable rate. This is particularly true for high-density memory devices such as dynamic random access memories (DRAMs). The increase in storage capacity is due to a number of factors, including advancements in processing technology and/or reductions in the size of various features within a DRAM. Reduced features include smaller spacings between repeated structures (smaller xe2x80x9cpitchxe2x80x9d), as well as reductions in the size of particular components, such as conductive line widths, transistors, capacitors, and the like.
Due to the great number of memory cells and high complexity of most semiconductor memory devices, it can be very difficult to consistently manufacture devices that are completely free of defects. If all semiconductor devices having defects were completely discarded, the manufacturing yield of such devices would be significantly lowered. In order to increase fabrication yield, most semiconductor devices include some sort of redundancy scheme.
A redundancy circuit typically replaces one circuit element (such as a defective memory cell) with another (such as a redundant memory cell). In operation, when an address is applied to a memory device that corresponds to a defective memory cell, a redundancy circuit can detect such an address and prevent the defective memory cell from being accessed. Instead, the redundancy circuit can provide access to a redundant memory cell. An access to a redundant memory cell can be indistinguishable from an access to a xe2x80x9cnormalxe2x80x9d memory cell.
In this way, even if a semiconductor memory device includes defective memory cells (due to uncontrollable process variation, for example), it can still be fully functional through the use of redundancy circuits. This can allow semiconductor devices with defective memory cells to be packaged and provided as working devices. Consequently, the overall fabrication yield can be increased.
As noted above, a redundancy circuit can continuously monitor externally applied address values. Such external address values can be compared with known defective addresses (addresses corresponding to defective memory cells) to determine when an access should be switched to a redundant memory cell. Information for identifying defective addresses is typically stored in a programming circuit. Many programming circuits include fusible links (fuses) for storing defective address information.
An example of a programming circuit is set forth in Japanese Laid Open Patent Application No. 8-96594. In the programming circuit of Japanese Laid Open Patent Application No. 8-96594, two fuse elements are allocated for each bit of an applied external address. According to the defective address bit value, one of the two fuses is opened. Thus, for each bit of a defective address, one of two fuses will be opened to thereby xe2x80x9cstorexe2x80x9d the defective address for the redundancy circuit.
A drawback to the approach set forth in Japanese Laid Open Patent Application No. 8-56594 is that two fuses are required for each address bit. For example, if a semiconductor memory device received a 10-bit address, 20 fuses would be required to program one defective address. Consequently, in a semiconductor device that is capable of replacing 1,024 defective addresses, as many as 2,048 fuses would be required. Fuses are typically devices of relatively large width. Thus, a large number of fuses can increase the overall area of a memory device. Such increases in area can translate into higher manufacturing costs.
One way to overcome the above drawbacks is to provide one bit for programming each defective address bit. In such an approach, the values of defective addresses are first determined. A circuit for each bit is then provided that includes a fuse and a volatile hold circuit, such as a flip-flop, or the like. Upon power-up (when power is initially applied to the semiconductor memory device) the volatile hold circuit will store a xe2x80x9c0xe2x80x9d or a xe2x80x9c1xe2x80x9d according to whether the corresponding fuse is opened or not. In this way, only one fuse can be required for each bit of a defective address. Thus, the number fuses can be reduced by half, saving considerable area.
The above-described method, that utilizes one fuse per address bit, differs from the approach shown in Japanese Laid Open Patent Application No. 8-56594 in that the application of power is required to set the defective address values. The application of power in such an xe2x80x9cinitial settingxe2x80x9d operation results in the formation of current paths through the fuse/hold circuit combinations. More particularly, current can flow through a current path and volatile circuit according to whether the corresponding fuse is opened or not. Consequently, a setting operation can draw a substantial amount of transient current. Still further, because the amount of current drawn is proportional to the number of fuses, the more defective addresses there are, the more transient current will be drawn in an initial setting operation.
As noted above, the number of memory cells in a semiconductor device continues to increase each year. Correspondingly, the number of defective memory cells can also increase. In order to maintain high yields, it may be necessary to construct redundancy circuits to address the increasing numbers of defective memory cells. It is thus expected that larger and larger numbers of programming circuits will be needed.
Because the number of programming circuits is expected to increase with higher density memories, the resulting transient current is also expected to increase. At the same time, the power supply requirements for semiconductor memories is not expected to increase, or is expected to increase at a slower rate. This is due to various power conservation techniques, such as dividing a memory into separately activated banks or blocks. Consequently, the power supply specifications may have limited current supplying capabilities, and transient current on power up can become a significant factor in design.
It may be that power supply requirements of a system may be sufficient to meet the transient current requirements resulting from increased numbers of programming circuits. However, such larger current requirements may still present drawbacks in other stages of manufacturing. For example, current requirements can be an important factor when a device is tested prior to being shipped. More particularly, many manufacturing operations can include an accelerated testing step that can detect devices that might fail over time.
Many accelerated testing approaches include mounting a large number of devices on a test board. Such devices can be tested at a lower speed than normal operating speeds. At lower testing speeds, semiconductor devices can draw less instantaneous and/or transient current. Consequently, test boards and corresponding equipment can have limited current supplying capabilities. However, higher density devices having larger numbers of programming circuits may require more current than a typical test board can provide. Consequently, a special, usually more costly, test board must be built to supply the higher start-up current of such devices.
It would be desirable to arrive at some way of providing a semiconductor device having programming circuits for redundancy circuits that does not have as a high a start-up transient current as conventional approaches.
According to one embodiment of the present invention, an address setting circuit may include a first fuse element group in which at least one first defective address may be stored, and a second fuse element group in which at least one second defective address may be stored. A timing circuit can enable current paths through the first and second fuse element groups at substantially different times, distributing transient current over time, and thereby reducing peak current.
According to one aspect of the embodiments, a redundant address setting circuit may include a group of fuse elements corresponding to a defective address. A timing circuit can enable current paths through one portion of the fuse elements at one time, and though another portion of the fuse elements at another time.
According to another aspect of the embodiments, a redundant address setting circuit may include a first latch circuit, a second latch circuit, and a timing signal generator circuit. The first latch circuit may include a first nonvolatile element that stores first defective address information, a first volatile storage circuit that stores the first defective address information from the first nonvolatile element, and a first setting circuit that transfers the first defective address information from the first nonvolatile element to the first volatile storage circuit in response to a first control signal. The second latch circuit may include a second nonvolatile element that stores second defective address information, a second volatile storage circuit that stores the second defective address information from the second nonvolatile element, and a second setting circuit that transfers the second defective address information from the second nonvolatile element to the second volatile storage circuit in response to a second control signal. The timing signal generating circuit can activate the second control signal after the first control signal.
According to another aspect of the embodiments, a semiconductor memory device may include a memory cell array having a number of memory cells, a redundant memory cell array having redundant memory cells, a selection circuit that selects a memory cell based on an applied address, and a redundancy decoder. In response to a defective address, the redundancy decoder can inhibit the operation of the selection circuit and select a redundant memory cell from the redundant memory cell array. The redundancy decoder may include nonvolatile memory elements, volatile memory elements, and setting circuits. The nonvolatile memory elements may store information for a number of defective addresses. The setting circuits can transfer the information stored in the nonvolatile memory elements to the volatile memory elements in response to at least two fuse reset signals. The setting circuits can transfer one portion of the information stored in the nonvolatile memory elements to volatile memory elements during a first period of time, and another portion of the information stored in the nonvolatile memory elements to volatile memory elements during a second period of time that is different than the first period of time.